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74ACT2708 64 x 9 First-In, First-Out Memory
February 1989 Revised January 1999
74ACT2708 64 x 9 First-In, First-Out Memory
General Description
The ACT2708 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data rate makes it ideal for high-speed applications. It uses a dual port RAM architecture with pointer logic to achieve the high speed with negligible fallthrough time. Separate Shift-In (SI) and Shift-Out (SO) clocks control the use of synchronous or asynchronous write or read. Other controls include a Master Reset (MR) and Output Enable (OE) for initializing the internal registers and allowing the data outputs to be 3-STATE. Input Ready (IR) and Output Ready (OR) signal when the FIFO is ready for I/O operations. The status flags HF and FULL indicate when the FIFO is full, empty or half full. The FIFO can be expanded to provide different word lengths by tying off unused data inputs.
Features
s 64-words by 9-bit dual port RAM organization s 85 MHz shift-in, 60 MHz shift-out data rate, typical s Expandable in word width only s TTL-compatible inputs s Asynchronous or synchronous operation s Asynchronous master reset s Outputs source/sink 8 mA s 3-STATE outputs s Full ESD protection s Input and output pins directly in line for easy board layout s TRW 1030 work-alike operation
Applications
* High-speed disk or tape controllers * A/D output buffers * High-speed graphics pixel buffer * Video time base correction * Digital filtering
Ordering Code:
Order Number 74ACT2708PC Package Number N28B Package Description 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for DIP
Pin Descriptions
Pin Names D0-D8 MR OE SI SO IR OR HF FULL O0-O8 Description Data Inputs Master Reset Output Enable Input Shift-In Shift-Out Input Ready Output Ready Half Full Flag Full Flag Data Outputs
FACTTM is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS010144.prf
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74ACT2708
Logic Symbol
Block Diagram
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74ACT2708
Functional Description INPUTS
Data Inputs (D0-D8) Data inputs for 9-bit wide data are TTL-compatible. Word width can be reduced by trying unused inputs to ground and leaving the corresponding outputs open. Reset (MR) Reset is accomplished by pulsing the MR input LOW. During normal operation MR is HIGH. A reset is required after power up to guarantee correct operation. On reset, the data outputs go LOW, IR goes HIGH, OR goes LOW, FH and FULL go LOW. During reset, both internal read and write pointers are set to the first location in the array. Shift-In (SI) Data is written into the FIFO by pulsing SI HIGH. When Shift-In goes HIGH, the data is loaded into an internal data latch. Data setup and hold times need to be adhered to with respect to the falling edge of SI. The write cycle is complete after the falling edge of SI. The shift-in is independent of any ongoing shift-out operation. After the first word has been written into the FIFO, the falling edge of SI makes HF go HIGH, indicating a non-empty FIFO. The first data word appears at the output after the falling edge of SI. After half the memory is filled, the next rising edge of SI makes FULL go HIGH indicating a half-full FIFO. When the FIFO is full, any further shift-ins are disabled. When the FIFO is empty and OE is LOW, the falling edge of the first SI will cause the first data word just shifted-in to appear at the output, even though SO may be LOW. Shift-Out (SO) Data is read from the FIFO by the Shift-Out signal provided the FIFO is not empty. SO going HIGH causes OR to go LOW indicating that output stage is busy. On the falling edge of SO, new data reaches the output after propagation delay tD. If the last data has been shifted-out of the memory, OR continues to remain LOW, and the last word shifted-out remains on the output pins. Output Enable (OE) OE LOW enables the 3-STATE output buffers. When OE is HIGH, the outputs are in a 3-STATE mode. Inputs MR H L SI X X SO X X IR X H OR X L Half-Full (HF) This status flag along with the FULL status flag indicates the degree of fullness of the FIFO. On reset, HF is LOW; it rises on the falling edge of the first SI. The rising edge of the SI pulse that fills up the FIFO makes HF go LOW. Going from the empty to the full state with SO LOW, the falling edge of the first SI causes HF to go HIGH, the rising edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. When the FIFO is full, HF is LOW and the falling edge of the first shift-out causes HF to go HIGH indicating a "nonfull" FIFO. Full Flag (FULL) This status flag along with the HF status flag indicates the degree of fullness of the FIFO. On reset, FULL is LOW. When half the memory is filled, on the rising edge of the next SI, the FULL flag goes HIGH. It remains set until the difference between the write pointer and the read pointer is less than or equal to one-half of the total memory of the device. The FULL flag then goes LOW on the rising edge of the next SO. Status Flags Truth Table HF L L H H FULL L H L H Full <32 Locations Filled 32 Locations Filled Status Flag Condition Empty
H = HIGH Voltage Level L = LOW Voltage Level
Reset Truth Table Outputs HF X L FULL X L O0-O8 X L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
OUTPUTS
Data Outputs (O0-O8) Data outputs are enabled when OE is LOW and in the 3STATE condition when OE is HIGH. Input Ready (IR) IR HIGH indicates data can be shifted-in. When SI goes HIGH, IR goes LOW, indicating input stage is busy. IR stays LOW when the FIFO is full and goes HIGH after the falling edge of the first shift-out. Output Ready (OR) OR HIGH indicates data can be shifted-out from the FIFO. When SO goes HIGH, OR goes LOW, indicating output stage is busy. OR is LOW when the FIFO is reset or empty and goes HIGH after the falling edge of the first shift-in. 3 www.fairchildsemi.com
74ACT2708
MODES OF OPERATION
Mode 1: Shift in Sequence for FIFO Empty to Full Sequence of Operation 1. Input Ready is initially HIGH; HF and FULL flags are LOW. The FIFO is empty and prepared for valid data. OR is LOW indicating that the FIFO is not yet ready to output data. 2. Shift-In is set HIGH, and data is loaded into the FIFO. Data has to be settled ts before the falling edge of SI and held th after. 3. Input Ready (IR) goes LOW propagation delay tIR after SI goes HIGH: input stage is busy. 4. Shift-In is set LOW; IR goes HIGH indicating the FIFO is ready for additional data. Data just shifted-in arrives at output propagation delay tOD5 after SI falls. OR goes HIGH propagation delay tIOR after SI goes LOW, indicating the FIFO has valid data on its outputs. HF goes HIGH propagation delay tIEafter SI falls, indicating the FIFO is no longer empty. 5. The process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes HIGH propagation delay tIHF after SI, indicating a half-full FIFO. HF goes LOW propagation delay tIF after the rising edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled.
Note: SO and OE are LOW; MR is HIGH.
FIGURE 1. Modes of Operation Mode 1
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74ACT2708
Mode 2: Master Reset Sequence of Operation 1. Input and Output Ready, HF and FULL can be in any state before the reset sequence with Master Reset (MR) HIGH. 2. Master Reset goes LOW and clears the FIFO, setting up all essential internal states. Master Reset must be LOW pulse width tMRW before rising again. 3. Master Reset rises.
4. IR rises (if not HIGH already) to indicate ready to write state recovery time tMRIRH after the falling edge of MR. Both HF and FULL will go LOW indicating an empty FIFO, occurring recovery times tMRE and tMRO respectively after the falling edge of MR. OR falls recovery time tMRORL after MR falls. Data at outputs goes LOW recovery time tMRONL after MR goes LOW. 5. Shift-In can be taken HIGH after a minimum recovery time tMRSIH after MR goes HIGH.
FIGURE 2. Mode of Operation Mode 2
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74ACT2708
Mode 3: With FIFO Full, Shift-In is Held HIGH in Anticipation of an Empty Location Sequence of Operation 1. The FIFO is initially full and Shift-In goes HIGH. OR is initially HIGH. Shift-Out is LOW. IR is LOW. 2. Shift-Out is pulsed HIGH, Shift-Out pulse propagates and the first data word is latched on the rising edge of SO. OR falls on this edge. On the falling edge of SO, the second data word appears after propagation delay
tD. New data is written into the FIFO after SO goes LOW. 3. Input Ready goes HIGH one fall-through time, tFT, after the falling edge of SO. Also, HF goes HIGH one tOF after SO falls, indicating that the FIFO is no longer full. 4. IR returns LOW pulse width t IP after rising and shifting new data in. Also, HF returns LOW pulse width t3F after rising, indicating the FIFO is once more full. 5. Shift-In is brought LOW to complete the shift-in process and maintain normal operation.
Note: MR and FULL are HIGH; OE is LOW.
FIGURE 3. Modes of Operation Mode 3
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74ACT2708
Mode 4: Shift-Out Sequence, FIFO Full to Empty Sequence of Operation 1. FIFO is initially full and OR is HIGH, indicating valid data is at the output. IR is LOW. 2. SO goes HIGH, resulting in OR going LOW one propagation delay, tOR, after SO rises. OR LOW indicates output stage is busy. 3. SO goes LOW, new data reaches output one propagation delay, tD, after SO falls; OR goes HIGH one propagation delay, tOR, after SO falls and HF rises one
propagation delay, tOF, after SO falls. IR rises one fallthrough time, tFT, after SO falls. 4. Repeat process through the 64th SO pulse. FULL flag goes LOW one propagation delay, tOHF, after the rising edge of 33rd SO, indicating that the FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW one propagation delay, tOE, after SO, indicating the FIFO is empty. The SO pulse may rise and fall again with an attempt to unload an empty FIFO. This results in no change in the data on the outputs as the 64th word stays latched.
Note: SI and OE are LOW; MR is HIGH; D0-D8 are immaterial.
FIGURE 4. Modes of Operation Mode 4
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74ACT2708
Mode 5: With FIFO Empty, Shift-Out is Held HIGH in Anticipation of Data Sequence of Operation 1. FIFO is initially empty; Shift-Out goes HIGH. 2. Shift-In pulse loads data into the FIFO and IR falls. HF rises propagation delay tX1 after the falling edge of SI. 3. OR rises a fall-through time of tFTO after the falling edge of Shift-In, indicating that new data is ready to be output.
4. Data arrives at output one propagation delay, tOD5, after the falling edge of Shift-In. 5. OR goes LOW pulse width tOP after rising and HF goes LOW pulse width tX3 after rising, indicating that the FIFO is empty once more. 6. Shift-Out goes LOW, necessary to complete the ShiftOut process.
Note: FULL is LOW; MRis HIGH; OE is LOW; tDOF = tFTO - tOD5. Data output transition--valid data arrives at output stage tDOF after OR is HIGH.
FIGURE 5. Modes of Operation Mode 5
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74ACT2708
FIFO Expansion
Word Width Expansion Word width can be increased by connecting the corresponding input control signals of multiple devices. Flags can be monitored to obtain a composite signal by ANDing the corresponding flags.
Note: AND the corresponding flags to obtain a composite signal.
FIGURE 6. Word Width Expansion--64 x 18 FIFO
Vmi = 50% VDD for AC/ACQ devices; 1.5V for ACT/ACTQ devices Vmo = 50% VDD for AC/ACT, ACQ/ACTQ devices
Vmi = 50% VDD for AC/ACQ devices; 1.5V for ACT/ACTQ devices Vmo = 50% VDD for AC/ACT, ACQ/ACTQ devices
FIGURE 7. 3-STATE Output Low Enable and Disable Times for AC/ACT, ACQ/ACTQ
FIGURE 8. 3-STATE Output High Enable and Disable Times for AC/ACT, ACQ/ACTQ
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74ACT2708
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) 32 mA -65C to +150C 32 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Junction Temperature (TJ) PDIP 140C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns
DC Electrical Characteristics
Symbol Parameter V CC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC ICCD Maximum Input Maximum 3-STATE Current Maximum ICC/Input Maximum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current Supply Current 20 MHz Loaded
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Test load 50 pF, 500 to ground
TA = 25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.5 0.6 1.0
TA = -40 to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4
Units
Conditions VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC -0.1V
V
V
IOUT = -50 A VIN = VIL or VIH
3.76 4.76 0.1 0.1
V V
IOH = -8 mA I OH = -8 mA (Note 2) IOUT = 50 A VIN = VIL or VIH
0.44 0.44 1.0 5.0 1.5 32 -32
V A A mA mA mA A mA
IOL = 8 mA IOL = 8 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC -2.1V VOLD = 1.65V VOHD = 3.85V VIN = VCC or GND f = 20 MHz (Note 4)
5.5 5.5 5.5 5.5 5.5 5.5 5.5 125
8.0 150
80 150
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74ACT2708
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 5) tPLH Propagation Delay, tIR SI to IR tPHL Propagation Delay, tIR SI to IR tPLH Propagation Delay, tIHF SI to > HF tPHL Propagation Delay, tIF SI to Full Condition tPLH Propagation Delay, tIE SI to Not Empty tPLH Propagation Delay, tIOR SI to OR tPLH Propagation Delay tMRIRH MR to IR tPHL Propagation Delay, tMRORL MR to OR tPHL Propagation Delay, tMRO MR to Full Flag tPHL Propagation Delay, tMRE MR to HF Flag tPHL Propagation Delay, tMRONL MR to On, LOW tPLH Propagation Delay, tD SO to Data Out tPHL Propagation Delay, tD SO to Data Out tPHL Propagation Delay, tOHF SO to < HF tPLH Propagation Delay, tOF SO to Not Full tPLH, tPHL Propagation Delay, tOR SO to OR tPHL Propagation Delay, tOE SO to Empty tPLH Propagation Delay, tOD5 SI to New Data Out tPHL Propagation Delay, tOD5 SI to New Data Out tPLH Propagation Delay, tX1 SI to HF tPLH Fall-Through Time, tFTO SI to OR tW R Pulse Width, tOP 5.0 12.5 17.0 26.0 12.5 30.5 ns 5.0 3.5 13.5 21.0 1.5 24.0 ns 5.0 3.5 10.0 16.0 2.5 18.0 ns 5.0 7.0 19.0 29.5 6.0 34.5 ns 5.0 7.0 19.0 30.5 6.0 35.5 ns 5.0 3.5 9.5 15.5 3.0 17.5 ns 5.0 2.5 7.0 11.5 2.5 13.5 ns 5.0 5.0 12.5 19.5 5.0 22.0 ns 5.0 3.5 8.5 13.5 3.5 15.5 ns 5.0 6.5 18.5 29.5 6.5 34.5 ns 5.0 6.5 18.5 27.0 6.5 31.0 ns 5.0 3.0 9.0 15.0 3.0 17.0 ns 5.0 8.0 17.5 27.5 8.0 30.5 ns 5.0 3.5 9.0 14.0 3.5 16.0 ns 5.0 7.0 16.5 25.5 7.0 29.0 ns 5.0 3.0 8.5 13.5 3.0 15.5 ns 5.0 4.0 13.5 16.5 4.0 19.0 ns 5.0 4.0 10.0 15.5 4.0 17.5 ns 5.0 4.5 10.5 16.5 4.5 19.5 ns 5.0 4.0 10.5 17.0 4.0 19.5 ns 5.0 2.0 6.5 11.0 1.5 12.0 ns 5.0 Min 2.0 TA = +25C CL = 50 pF Typ 6.5 Max 11.0 TA = -40C to +85C CL = 50 pF Min 1.5 Max 12.5 ns Units
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74ACT2708
AC Electrical Characteristics
(Continued)
TA = +25C CL = 50 pF Min 14.5 16.5 17.5 6.0 Typ 20.5 28.0 30.0 15.0 Max 30.5 43.0 46.5 23.5 TA = -40C to +85C CL = 50 pF Min 14.5 16.5 17.5 2.5 Max 36.5 51.5 56.0 28.0 ns ns ns ns Units
VCC Symbol Parameter (V) (Note 5) tW tW tW tPLH HF Pulse Width, tX3 IR Pulse Width, tIP HF Pulse Width, t3F Fall-Through Times, tFT SO to IR tPZL Output Enable OE to On tPLZ Output Disable OE to On tPZH Output Enable OE to On tPHZ Output Disable OE to On fSI Maximum SI Clock Frequency fSO Maximum SO Clock Frequency
Note 5: Voltage Range 5.0 is 5.0V 0.5V
5.0 5.0 5.0 5.0
5.0
2.0
6.5
11.0
1.5
12.0
ns
5.0
1.5
5.0
8.5
1.5
9.5
ns
5.0
2.0
7.0
12.0
1.5
13.0
ns
5.0
1.5
7.0
12.0
1.5
13.0
ns
5.0
55
85
45
MHz
5.0
42
60
35
MHz
AC Operating Requirements
VCC Symbol Parameter (V) (Note 6) tW(H) tW(L) SI Pulse Width, tSIH SI Pulse Width, tSIL 5.0 5.0 TA = +25C CL = 50 pF Typ 3.5 6.0 6.5 10.0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 7.5 12.0 ns ns Units
tS
Setup Time, HIGH or LOW, Dn to SI
5.0
1.0
3.5
4.5
ns
tH
Hold Time, HIGH or LOW, Dn to SI
5.0
1.5
3.5
4.5
ns
tW trec
MR Pulse Width, tMRW Recovery Time, tMRSIH MR to SI
5.0 5.0
13.0 4.5
20.0 7.5
24.5 8.5
ns ns
tW(H) tW(L)
SO Pulse Width, tSOH SO Pulse Width, tSOL
5.0 5.0
7.5 9.0
6.5 14.0
8.0 17.0
ns ns
Note 6: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 20.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V
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74ACT2708 64 x 9 First-In, First-Out Memory
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide Package Number N28B
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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